In general, you should not be getting errors when you compile a project, and there is usually something to fix. Read the entire message carefully -- it is more useful than students usually realize.
Warnings are another matter. Unfortunately, the lab manual instructions sometimes (as in the tutorial) tell students that they should not get warnings, but that is not necessarily true, even for those early designs. There are really two reasons why you may be getting warnings even when the instructions say you should not:

1. Software updates changed the warnings that are produced by Quartus, since the instructions were written.
2. User preferences in a particular Quartus installation may have changed which severity of warnings are hidden or displayed.

The few warnings that show up in the tutorial are probably not an issue. That actually answers the main question most students have about warnings. But some students actually want to know more about the common warnings, so read on.

• Found [nn] output pins without output pin load capacitance assignment. -- This almost always occurs. It's beyond the scope of this course, but even though the FPGA pins are TTL compatible, producing the correct high and low logic levels, it really depends on what exactly is connected to the FPGA pins.  The DE2 board was designed by people who knew what they were doing.  Quartus doesn't know your target FPGA is on a board designed by people who knew what they were doing.  It is warning you that you haven't given it detailed information that would allow it to calculate if the outputs will change as fast as they should. (Higher capacitance on a pin means more electrons have to flow to make the voltage change, and it takes longer.)
• Not all pins in bus "SW[17..0]" are used.  (Or some other signal besides SW, with some other pin number range).  This means exactly what it says.  You seem to have wanted to use some pins that have a meaningful group, but you left some out. Quartus wants you to make sure that's what you meant.
• Warning: Design contains nnn input pin(s) that do not drive logic. Quartus knows about some input pins, but doesn't see where they are actually used.  The most common occurrence is the one mentoned above.  It could be an indication of a real problem, though (for example), where you added an input pin for something called CLOCK, never actually used it, and connected the CLOCK input on your flip flops to something entirely wrong.   It would compile with no errors, because the CLOCK inputs were driven by something. But it wouldn't be what you intended.
• Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.  You don't need this feature. You don't need a lot of the capability of Quartus, for that matter.  There's no time to learn it in one semester.
• Warning: Ignored locations or region assignments to the following nodes. Later, students may be provided with project files where some of the work of assigning pins has been done for them.  There may be some pins assigned that aren't actually used in the design project.  Quartus is telling you about that.
• Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Related to the previous.
• Warning: Using design file filename.ext, which is not specified as a design file for the current project, but contains definitions for nnn design units and mmm entities in project . Ideally, when you have a project with multiple design files (a hierarchical design with a top-level file and various files "inside" that), you have taken care to specifically add every file to the project (in the Project Navigator "Files" window pane, or under "Project...Add/Remove Files..."   If you don't do that, but if the needed design files are right there in the folder where Quartus expects them, it will compile successfully and give you this warning that you didn't do the Add Files thing.